Advanced Packaging

advanced packaging technologies

Process and Equipment Solutions for Advanced Packaging Fabs

To reduce power consumption and conserve space, integrated circuit and MEMS device manufacturers have developed various advanced packaging technologies. Among these Wafer Level Packaging (WLP) technologies are Through Silicon Via (3D/TSV), bonding, bumping, pillars, etc.

Each of these techniques requires unique and specific process solutions to assure consistently high yields. Depending on your requirements we have the equipment including the Velocity single wafer and GAMA batch immersion systems to meet your process needs. The below listed are examples of the technologies NAURA Akrion employs to assure excellent device performance.

Cleaning after DRIE (Deep Reactive Ion Etching)

Megasonics drive chemicals deep into vias (60 nm) for efficient polymer removal eliminating C and O residue. Our system eliminates device failures caused by voiding after CVD deposition by removing: Si-C based polymer at bottom of scallop-shaped side wall and C-F polymer residue at the side walls.

Resist Removal

NAURA Akrion has developed process solutions that utilize megasonics to enhance the removal of thick resists using industry standard chemistry while significantly reducing the process times and amount of chemicals used thereby saving you money.

Deep Feature Processing

Wafers with very high aspect ratio features are creating issues for traditional wet process techniques. Air pockets are formed that prevent uniform wetting resulting in miss-processing. NAURA Akrion has developed technologies to enable these wafers to be properly etched, cleaned and dried.

Glass Wafer Cleaning

GAMA series and V3 systems are available to handle Resist Strip, Pre-clean after Strip and Final Clean applications for mask/glass plate manufacturers. V3 is best used for low volume manufacturing or pilot line/R&D use, while GAMA is the high throughput, high volume equipment solution.